1. Field of the Invention
The present invention relates to debug and testing of computer systems, specifically, for detecting hang or dead lock conditions.
2. Description of the Related Art
As the technology for manufacturing integrated circuits advances and demand for increased processor and memory performance, the debugging and testing integrated devices have significantly become more complex. Modern integrated circuit (IC) devices include large numbers of gates on a single semiconductor chip. As the complexity of the ICs increase, so does the cost and complexity of verifying/debugging functionality and electrically testing the individual IC and the systems in which they are employed. Testing and manufacturing costs and design complexity increase dramatically because of new manufacturing processes and new interconnect technologies.
One example of debugging system functionality is detecting a hang conditions, which can also be classified as dead lock logic bugs. A deadlock is a circular set of dependencies where one logic block is waiting for a second logic block, which is waiting for the first. A front side bus logic analyzer system has an easy to detect indicator of bus hang. In contrast, point-to-point architecture systems and trace data may be distributed on 8 to 10 logic analyzer trace instruments in 4 socket systems. As the symptom of a hang can be from any socket on any port, potentially any/all link pair(s) might need to be set up for cross triggering.
Traditional logic analyzers do not transform the data in real time for a compressed view of data traffic from multiple buses or logic analyzers. They can only filter but not transform the data. Therefore, present solutions for detecting the hang condition are not feasible.